In today's high speed networks, such as 100 Gigabit (100 G) and 400 Gigabit (400 G) Ethernet networks, data is scrambled with a scramble key before being transmitted on the wire to reduce undesirable frequency characteristics and to facilitate descrambling at the receiver. For example, transmitting a long sequence of ones or zeros results in spikes at specific frequencies and inefficiently utilizes the frequency bandwidth allocated for the transmitted signal. In addition, a long sequence of ones or zeros makes synchronization at the receiver difficult due to the lack of transitions in the transmitted signal. Transmitters use a scramble key and a corresponding scrambling algorithm to reduce the likelihood of long sequences of ones and zeros and thereby spread the frequency spectrum of the transmitted signal over a wider frequency bandwidth.
Scrambling data at line rates in high speed networks can be difficult. In 100 G Ethernet, 400 G Ethernet, and beyond, data bus widths can be on the order of hundreds of bits in order to transmit data at line rates. Scrambling data at line rate on such wide busses requires that an entire bus width of data be scrambled during each clock cycle. Scrambling an entire bus width of data when the bus is on the order of hundreds of bits wide requires that the scrambler logically implement the shift and XOR operations for each bit on the data bus being scrambled. While such logic implementations are possible, physical real estate on a chip for implementing a scrambler may be limited.
Accordingly, there exists a long felt need for methods, systems, and computer readable media for efficiently implementing a scrambler for scrambling data in high speed communications networks.